VLSI: designing electronic chips

Designing the chips themselves, rather building things out of chips.

updated 2003-02-08

This page is about designing things are being built today; see also nanotechnology for some thoughts about the ultimate future and limits of MEMS -- things that seem likely to be designed within another lifetime.

This file contains pointers to vlsi design guides and software.


David also maintains related files:


I'm thinking about moving this whole page to a wiki. I found on VLSI wiki for a particular class. Is there a better wiki for VLSI stuff ?

General electronic comments

Typically the electronics part of a system is partitioned into 4 parts, with no 2 parts residing on the same chip.

  1. hi-power, hi-voltage circuits.
  2. low-level analog signal processing
  3. custom (random) control logic
  4. (regular) datapath logic
  5. (very regular) fast memory
  6. (very regular) slow memory

Anything that could be implemented at one level of this list can also be implemented at higher levels; but generally, when you have large numbers of something you want to do, and these things don't really require the ultimate in speed/power, it's far cheaper to migrate those functions to a lower level on this list, because these things are so regular you can generally find off-the-shelf chips that already to that. On the other hand, when you want a system to go faster, you typically find the bottleneck in the system (a few locations of slow memory, a few parts of the datapath, a few common sequences of the control logic) and move them to a higher level. (at the start of 1998, the bottleneck in most desktop CPUs was slow virtual memory; adding more DRAM had the best performance_increase/cost ratio).

A typical system has far more "stuff" (countable things) at lower levels of this list than at higher levels (even though they may sometimes have roughly equivalent physical areas, since the regular structures lower on the list can pack together much more tightly).

Once upon a time the (3) and (4) were always partitioned into separate chips; now it's invariably stuck all in one chip (CPU, MPU, DSP); sometimes we see 2 chips in a system that both have mixtures of this (a CPU and a FPGA).

The trend continues to try to keep merging consecutive levels on a single chip. For example,

The ultimate extension of this trend is, of course, to merge all functions all on one chip -- "systems-on-a-chip". In fact, some of the most interesting "chips" out there try to add mechanical and chemical functionality to a chip -- -- this is generally called MEMS.

On the other hand, the memory levels (5 and 6) seem to keep diversifying -- -- many of the fastest systems have a "multi-level memory architecture" with 4 different levels of memory -- "Virtual memory" on magnetic media, "physical memory" in DRAM, L2 cache in SRAM, and L1 cache integrated on the CPU.

VLSI design tools

Layout editors and related tools for chip design (control logic and datapath logic); papers about the design process.

The most famous is the freeware Magic.

The general types / categories of design tools for designing either very large scale integrated (VLSI) devices or printed wiring board (PWB).

Specific Software

VLSI designs

VLSI designs: some specific implementations.

photographs of chips

Also libraries that might come in useful for your design.

low power design

[FIXME: I thought I had lots of links to pictures of various low power designs....]

see also


Micro Electro-Mechanical Systems (MEMS)

David Cary has a subscription to the _Journal of Microelectromechanical Systems: A Joint IEEE and ASME Publication on Microstructures, Microactuators, Microsensors, and Microsystems_ . This journal has lots of scanning-electron-microscope (SEM) photographs of actual MEMS.

Mems links:

clockless logic

clockless logic and the metastable state.

"NULL Convention Logic(TM) (NCL)(TM) ", a kind of "clockless logic", "self-timed logic", a alternative to "Clocked Boolean Logic (CBL)." Can be used in standard FPGAs. Because it doesn't need clocks, it promises to reduce power consumption.

Unfortunately, "the metastable state is the bane of asynchronous digital systems." A good explanation of the (surprising) problems this causes in asynchronous circuits (and why it is not a problem in clocked circuits) is in the book _Computation Structures_ by Ward and Halstead (section 4.6).

the metastable state

the metastable state

DRAM and other memory devices

technical notes and future trends (woefully incomplete)

This list mostly focuses on timing diagrams and ways to interface to commodity memory devices. Currently "EDO DRAM" is the most common memory interface. "FLASH RAM" is becoming popular for handheld devices.


see also Writing Device Drivers for some PCI-related software tools.

see also serialportdocs.html for lots of other communication buses including USB.

see also Universal Plug and Play http://www.upnp.org/ .

General Information about PCI:

specific PCI chips:

PCI development tools:

Using the UNIX Workstations at OSU

(flagrantly copied from the handout from Dr. L. G. Johnson ) (see also Oklahoma State University System on Chip (SoC) Design Flows for use with Magic, Cadence, Synopsys, and MOSIS http://avatar.ecen.okstate.edu/projects/scells/ )

tesla.ceatlabs.okstate.edu provides all unix-based CAD tools.

tacoma.ceatlabs.okstate.edu provides electronic mail services.

Access them from these facilities:

See the CEAT staff in EN302 for more information about these (except for the CIS machines).

If you don't have a direct connection, on your local X terminal type

	xhost tesla.ceatlabs.okstate.edu
	telnet tesla.ceatlabs.okstate.edu
	export DISPLAY

VLSI companies

includes both and , for

Companies that build straight digital logic ICs, analog ICs, and MEMs chips. This includes


For companies that design and manufacture FPGAs, see computer_architecture.html#FPGA

For companies that *use* chips in their designs (satellites, medical equipment, HDTV machine_vision.html#hdtv , etc), see link_farm.html#interesting_companies .

For companies that may make the silicon IC obsolete, see nanotech.html#company for companies doing genetic engineering, molecular digital logic, and quantum computing.

high_voltage.html lists a few more companies.

machine_vision.html lists companies that either (a) sell DSP chips fast enough to handle video data rates, or (b) sell CCD or CMOS image sensors. or both.

Computational RAM

The Berkeley Intelligent RAM (IRAM) project http://iram.cs.berkeley.edu/ seeks to understand the entire spectrum of issues involved in designing general-purpose computer systems that integrate a processor and DRAM onto a single chip - from circuits, VLSI design and architectures to compilers and operating systems. IRAM should offer several advantages over today's solutions, including considerably reduced latency and dramatically increased bandwidth to main memory, reduced power and energy consumption, and reduced space and weight for embedded, portable, desktop, and parallel computer systems.

[FIXME: f-cpu mailing list eGroup home: http://www.eGroups.com/list/f-cpu ]

[FIXME: is there a Wikipedia article on computational RAM yet? http://en.wikipedia.org/wiki/Iram ]

[start message] Date: 1999-04-06 To: transhumantech-l at excelsior.org, f-cpu at egroups.com From: David Cary <d.cary at ieee.org> Subject: Computational RAM Cc: Bcc: X-Attachments: Looks like some predictions by Eugene Leitl and others are already coming true. "Computational RAM: Implementing Processors in Memory" article by Elliot, Stumm, Snelgrove, Cojocaru, Mckenzie in _IEEE Design & Test of Computers_ http://computer.org 1999-01 p.32-41 :

Computational RAM is a processor-in-memory architecture that makes highly effective use of internal memory bandwidth by pitch-matching simple processing elements to memory columns. Computational RAM can function either as a conventional memory chip or as a SIMD (single-instruction-stream, multiple-data stream) computer. When used as a memory, computational RAM is competitive with conventional DRAM in terms of access time, packaging, and cost. As a SIMD computer, computational RAM can run suitable parallel applications thousands of times faster than a CPU. ...

... exploit the chip's wide internal data paths ... exploit the energy efficiencies that result from better utilization of memory bandwidth and localization of computations on a millimeter scale ...

... a host CPU can read and write to any memory location during an external memory cycle. ...

Memory Bandwidth
DRAM is organized with a very wide internal data path ... a 1Mx16 bit, 1K-cycle-refresh DRAM selects 16 Kbits with the 10 bit row address, and then one of 1 024 sixteen-bit words for output when the column address is available. ... the width of the internal data path is 1K ... times the width of the external data path. In systems with large amounts of memory, multiplexing banks of RAM onto a narrow bus limits bandwidth even further. ... cache improves the bandwidth [but] only by a factor of four, leaving a gap of three and a half orders of magnitude ...

... A more mainstream architectural alternative to pitch-matching processing elements to groups of sense amplifiers is to put a single RISC or vector processor in a DRAM chip. This [allows] conventional programs to be compiled and run .... [and] access to a wider bus (...256 bits) for cache or vector register fills than it would have if implemented on a separate chip. Still ... the 16 Kbit wide data path at the sense amplifiers multiplexes down by a factor of 64 or more. ...

Power consumption
Power consumption is rapidly becoming a key measure of merit of computer architecture ... An internal DRAM bus is much more energy efficient (as well as faster) than an external bus because shorter wires must be driven. ... We can save a sizeable portion [perhaps 1/2, depending strongly on access pattern] of the power by not driving signals off chip. ...

Computational RAM architecture
... We have implemented both designs in silicon ... 16 Mbit DRAM processes.

The simpler of the two processing elements ... supports bit-serial computation and has left, right, and wired-AND bused communication. The ALU [is] an 8-to-1 multiplexer ... we can implement an entire processing element (including the off-chip read/write path) with as few as 88 transistors ... The control signals (derived from a 13 bit SIMD instruction) are routed straight through a row of processing elements.

... The processing elements and support circuitry add 18% to the area of an existing DRAM design. A single processing element occupies an area of approximately 360 bits of memory (including the sense amplifier and decoder overhead). ...

Effects of DRAM technology
DRAM technology is quite different from the technologies usually used for processors ... processors use four or five layers. The difficulty is not technical, but economic: if the processor needs five layers of metal, the extra metal layers are wasted over the DRAM array. In a competing architecture that segregates processing and memory, the dominant silicon area devoted to memory will cost less.

The characteristics and operating conditions of DRAM transistors make them slower than transistors in an equivalent ASIC or digital logic process. ...

In any technology, a processing element has shorter lines and hence can cycle faster (and dissipate less power) than the DRAM array. This makes it practical to interpose two processor cycles in each memory cycle.

DRAM also relies heavily on redundancy to improve yield, which would otherwise be quite low due to high densities and large dies. Processors, on the other hand, are usually designed without redundancy ... since they occupy a small fraction of die area and therefore have limited effects on yield. ...

... The computational RAM philosophy is that largely sequential applications belong on the host, and the massively parallel component belongs in the memory. ...

3x3 convolution 16 M: C-RAM runtime: 17.6 ms; Sun Sparc runtime: 113 s; C-RAM speedup ratio: 6 404 ...

Incidentally, testing is another application for which computational RAM obtains a parallel speedup. The processing elements can be tested and then, themselves, perform the memory tests in less total time than it would take to test a similar-capacity memory. ...

Additional information about computational RAM is available at http://www.ee.ualberta.ca/~elliott/cram/ ...

Send comments and questions about this article to Duncan Elliot duncan.elliott@ualberta.ca

From a programming point of view, computational RAM seems very similar to the CAM-8 http://www.im.lcs.mit.edu/cam8.html . -- David Cary "mailto:d.cary@ieee.org" "icbmto:N36 08.830' W97 03.443'" http://www.rdrop.com/~cary/ Future Tech, Unknowns, machine vision ><> <*> O- [end message]

Date: Wed, 1 Apr 1998 05:17:14 -0500 (EST)
Comment: Hx: Transhuman Technlogies
Originator: transhumantech at excelsior.org
Reply-To: <transhumantech at excelsior.org>
Sender: transhumantech at excelsior.org
Version: Autolist v0.2 - Copyright 1995 Planet X Engineering
From: Eugene Leitl <eugene at liposome.genebee.msu.su>
To: Multiple recipients of list <transhumantech at excelsior.org>
Subject: beefing up a Beowulf ; smart memories almost here at last


                    Memory Module
                    (03/27/98; 10:55 a.m. EST)
                    By Stephan Ohr, EE Times

                    Engineers reacted with approval to Texas
                    Instruments's technology demonstration at
                    WinHec of DIMM memory modules
                    featuring embedded digital-signal
                    processors (DSPs). Called Basava, the
                    individual modules can fit in a standard
                    168-pin memory-module slot on a Pentium
                    II-based motherboard or into the 144-pin
                    slot in a portable computer. The module
                    looks and behaves like a standard
                    synchronous DRAM (SDRAM) bank to the
                    processor and operating system, but can be
                    awakened on command to rapidly perform a
                    high-Mips DSP task. When the task is
                    completed, the Basava returns to its role as a
                    dumb memory module.

                    Developed as an exercise at TI's Tsukuba
                    Research and Development Center in Japan,
                    the module is designed to offload
                    DSP-specific tasks from a Pentium II host.
                    A tight coupling of the DSP with SDRAM
                    improves performance, said Raj Pawate,
                    senior member of the technical staff at
                    Tsukuba. The module offers performance
                    that's almost an order-of-magnitude
                    improvement over DSP cards that rely on
                    the PCI bus to communicate data and
                    instructions. And it makes little impact on
                    system memory when DSP tasks are not
                    being performed.

                    The module uses a TMS320C6X DSP in its
                    168-pin version, and a TMS320C54X in its
                    144-pin version. The DSP is expected to
                    pop awake on command or on a cue from
                    the operating system. Then its first task is to
                    partition the memory on the module for
                    DSP tasks. While the entire 64 megabytes,
                    for example, of a DIMM might be available
                    while a DSP sleeps, the module might set 16
                    MB aside for use by the awakened DSP and
                    leave 48 MB for the Pentium II. In all cases,
                    the partitioning is to be transparent so that a
                    Pentium II host processor can continue its
                    tasks without interruption.

                    Pawate said that the Basava module has
                    already received electrical certification as a
                    memory module from the Electronic
                    Industries Association of Japan (EIAJ).
                    Software certification and operating system
                    support is also being sought from other
                    standards-making bodies and from

                    Basava will be particularly useful for audio
                    and video DSP tasks like DVD playback or
                    motion JPEG compression, said Pawate.

                    But engineers who had passed through TI's
                    booth at WinHec had imaginative ideas of
                    their own. "You need lots of bandwidth for
                    motion display," said Charles Marslett, a
                    consumer digital entertainment software
                    engineer with VLSI Technology, in Tempe,
                    Ariz. "But this would also help with system
                    debugging." Many large systems based on
                    gate arrays are difficult to simulate and test,
                    he volunteered.

                    Emulation tool vendors like Quickturn
                    Systems currently provide FPGA and
                    programmable-logic boards as targets for
                    gate-array development and simulation.
                    Basava could take their place, the engineer
                    said. "The DSP memory won't be as fast as
                    the Quickturn system," Marslett speculated,
                    "but it will be a lot smaller and cheaper."

See also:


3 GFlops/$50 by y2k.

binary arithmetic

clever methods and ways of representing numbers, building addition, subtraction, multiplication, etc. out of bits and gates.

Building more complicated things out of bits and gates. Starting with 8 bit bytes, addition, subtraction, etc.

See also

Once you have multiplication and division on integers, see 1d_design.html for building more complicated things: floating point, trig functions, etc.


Virtual Socket Interface Alliance (VSIA) http://www.vsi.org/ is working on a open, standard, on-chip bus; already has some standard on-chip bus alternatives on their web page A standard on-chip bus would greatly simplify designing "system on a chip" reusing existing designs.

Programmable Arithmetic Devices for High Speed Digital Signal Processing http://infopad.eecs.berkeley.edu/spartan/talks_papers/dchen_phd/thesis_html/thesis.html includes "Limitations of FPGAs" and a nice chart of frequency v. what sorts of devices can handle those frequencies. also "Logic and VLSI Implementation" of the PADDI ("Programmable Arithmetic Devices for High Speed Digital Signal Processing") architecture.

Sand Microelectronics http://www.sandmicro.com/ claims to be "the leading provider of intellectual property (IP) with a focus on industry standard bus interfaces such as PCI, USB and 1394."

MEMS http://dolphin.eng.uc.edu/

Potential Nanoelectronic Two-State Devices http://www.mitre.org/research/nanotech/potential2state.html includes a review of Conventional Microelectronic Two-State Devices, the limits to scalability they have, "the 0.1 micron barrier." and proposed new devices that can be made even smaller.

IDaSS: ASIC lay-out of a 'Peripheral Control Cell' processor core ("can be considered an 8 bit RISC machine.") http://www.eb.ele.tue.nl/proj/idass8x3.html Nice picture !

http://www.us.design-reuse.com/ claims to be "The world's largest directory of Virtual Components, Software and Services for designing systems on chip".

icBIST 3.0 embedded test technology "is said to result in significant reductions in test development and manufacturing test costs" ... at-speed test ... support for mixed-signal cores ... (integrated circuit Built In Self Test) ... Logicvision Inc. http://www.logicvision.com/

OptoMOS relays http://www.cpclare.com

http://www.mrc.uidaho.edu/vlsi/ many links to VLSI information, including job opportunities, ...

Chip people http://www.engr.uky.edu/EE/Stroud/people.html (chip images; screen-captures from Magic)

CPU Info Center http://infopad.EECS.Berkeley.EDU/CIC/ (info on low-power CPU design)

Smithsonian institute interview with Seymour Cray http://innovate.si.edu/history/cray/cray33.htm Aesthetics, "the liquid that we're using to cool our Cray 2's, Cray 3's, Cray 4's, is also used as artificial blood in human beings", a bit of nanotech, "focused on the thing" vs. "people person", the necessity of taking risks,

Physics of Computation (Physcmp), Carver Mead's group http://www.pcmp.caltech.edu/ lots of chip design pointers. [perhaps suggest irsim -- or ask if 'log' is superior in every way]

Computer Architecture newsgroups http://x1.dejanews.com/bg.xp?level=comp.arch

Berkeley Design Technology, Inc. http://www.bdti.com/ sells the "Buyer's Guide to DSP Processors" for a mere $ 2 450.

[vlsi] http://www.letu.edu/student/orgs/acm/minutes/Future.htm current and future chip technology [vlsi#mems] http://www.ee.surrey.ac.uk/Personal/D.Banks/usys_i.html MICROSYSTEMS, MICROSENSORS & MICROACTUATORS: An Introduction. Danny Banks. <D.Banks at surrey.ac.uk>


Exponential Technology http://www.exp.com/products/x704/bicmos.html "bipolar logic was widely acknowledged to be faster than CMOS, but most people believed it was impossible to use bipolar logic for a mainstream microprocessor because it required too much power and cost too much to manufacture. ... the X704TM, a PowerPCTM compatible microprocessor. ... With this new BiCMOS technology, the X704 utilizes both bipolar and CMOS technologies without compromising the bipolar transistors. As a result, the bipolar transistors are small enough and fast enough to be used for complex logic. ... "

VLSI TUTORIALS http://et.nmsu.edu/ETCLASSES/vlsi/AUTHOR.HTM by Sonia Champion Jeffrey Edaakie New Mexico State University http://et.nmsu.edu/ETCLASSES/vlsi/files/VLSI.HTM

[MEMS] http://imems.mcnc.org/imems/imems.html "the surface micromachining process integrated with BiCMOS electronics used by Analog Devices for its commercial accelerometers is available through MCNC for experimental project chip use by the general U.S. public"

http://www.cybercom.net/~ahvezda/ gEDA - GPL'd Electronic Design Automation tools, some FORTH info, lots of info on designing and building (!) (homebrew wire-wrapping, making PCB boards, programming PLDs, GALs, ROMS, FPGAs, and minimal 68K systems) your own CPU, bootstrapping a new system, and some Theory/Speculation on future computers. computer_architecture.html#forth

What is "Delay Calculation Language (DCL) IEEE 1481" ?

VLSI Microprocessors: A Guide to High-Performance Microprocessor Resources http://www.microprocessor.sscc.ru/

The Institute for Interconnecting and Packaging Electronic Circuits (IPC) http://www.ipc.org/

David Harris http://www.stanford.edu/~harrisd/ invented "Opportunistic Time-Borrowing Domino circuits" http://patent.womplex.ibm.com/cgi-bin/viewpat.cmd/5517136 while working for Intel.
Teaches High Speed CMOS Circuit Design (VLSI) at MIT
wrote (shareware) RoboWar for the Macintosh
has Skew-Tolerant Circuit Design (thesis draft) online.

the Scalable Coherent Interface (SCI) Users, Developers, and Manufacturers Association http://www.scizzl.com/ (ANSI/IEEE Std 1596)

The Scalable Coherent Interface (Local Area MultiProcessor) is effectively a combination computer backplane bus, processor memory bus, I/O bus, high performance switch, packet switch, ring, mesh, local area network, optical network, parallel bus, serial bus, information sharing and information communication system that provides distributed directory based cache coherency for a global shared memory model and uses electrical or fiber optic point-to-point unidirectional cables of various widths. Typical performance is currently in the range of 200 MByte/s/processor (CMOS) to 1000 MByte/s/processor (BiCMOS) over distances of tens of meters for electrical cables and kilometers for serial fibers. SCI/LAMP was designed to be interfaceable to common buses such as PCI, VME, Futurebus, Fastbus, etc., and to I/O connections such as ATM or FibreChannel. It was designed to work in complex multivendor systems that grow incrementally, a harder problem than interconnecting processors inside a single product (e.g. MPP). Its cache coherence scheme is comprehensive and robust, independent of the interconnect type or configuration, and can be handled entirely in hardware, providing distributed shared memory with transparent caching that improves performance by hiding the cost of remote data access, and eliminates the need for costly software cache management.

Viewlogic Systems, Inc. http://www.viewlogic.com/ "full suite of Design Entry, Enterprise, Simulation, FPGA and High Speed analysis products." electronic design software

Cavendish Laboratory Microelectronics Research Centre http://www.qdo.com/Exp/MRC1/

_HDI: The magazine for High-Density Interconnect_ http://www.hdi-online.com/ Free Subscription to the paper version http://www.hdi-online.com/forms/freesub.htm

Flip Chip Technologies, LLC http://www.flipchip.com/ has a Design Guide http://www.flipchip.com/flipsec7/desn.htm to help you design flip chip ICs compatible with their process.

[vlsi ? FreeCAD ?] ProperCAD Research Group Home Page http://www.crhc.uiuc.edu/ProperCAD/ "The ProperCAD project at the University of Illinois's Center for Reliable and High-Performance Computing is an investigation of the use of parallel computing resources for the most compute intensive VLSI CAD algorithms."

the laboratory of Professor Christof Koch http://www.klab.caltech.edu/ "Biophysics of Computation in Single Neurons", "Neuromorphic Analog VLSI Vision Systems", pretty visual illusions. http://www.illusionworks.com/

_Integrated System Design_ magazine http://www.netline.com/isd/

Topics covered in Integrated System Design include:

FPGA floor planning, clock and power distribution, low-power design, hardware-software codesign, ASIC prototyping, state machine design, design reuse, embedded system design, library development

Each issue contains a practical system, design story relating to such topics as:

set-top boxes, PDAs, graphics chips, medical electronics, networking systems, wireless communications

http://www.ece.ucdavis.edu/sscrl/ "The SSCRL Lab is located in 2201 Engineering Unit II on the UCDavis Campus. The lab is dedicated to designing, building and testing Integrated Circuits (ICs)." SSCRL maintains the comp.lsi.cad FAQ http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/

Synopsys, Inc. http://www.synopsys.com/

Analog Devices, Inc. http://www.analog.com/ "develops, manufactures and markets high-performance analog, digital, and mixed-signal integrated circuits (ICs) used in signal-processing applications." Has a nice online part search; lots of app notes online. Was the first company (I think) to commercially sell umachined MEMs devices -- their accelerometers.

Open-24-7.com http://www.open-24-7.com/ sells GaAs (gallium arsenide) and Si (silicon) wafers.

CSEM http://csem.ch/ sells MEMS accelerometers.

"CPLD design methods are moving to open languages like VHDL, Verilog, and Jam" "The Jam language is a freely licensed and open standard. Most of the source code required for the Jam Player is contained in the Jam Device Programming and Test Language Developer's Kit available at http://www.altera.com/ " also see http://www.jamisp.com/

_Solid State Technology: The International Magazine for Semiconductor Manufacturing_ http://www.solid-state.com/ (gives free subscriptions to qualified individuals)

Project: Von Neumann http://www.krl.caltech.edu/~charles/alife-game/ a freeware computer game, played with human and AI "probes" that learn.

ECE 474/574 http://www.ece.orst.edu/~ece474/ includes links to many sites with VHDL information, and some documentation on synthesis.

http://www.wkap.nl/ ???

http://www.tdes.com/ ???

http://www.prenhall.com/ ???

Open Verilog International http://www.ovi.org/

http://www.anasift.com/ ???

http://www.apteq.com/ ???


Advanced Micro Devices, Inc. http://www.amd.com/

"Enable Semiconductor has spun off its existing low-power IC business into a new privately held corporation, NanoAmp Solutions." -- http://www.techweb.com/wire/story/TWB19990304S0010

Switching from aluminum to copper was a big deal ( http://www.research.ibm.com/resources/magazine/1997/issue_4/copper497.html ). Why don't semiconductor manufacturers just use gold ?

comp.lang.vhdl http://www.dejanews.com/[ST_rn=bg]/dnquery.xp?query=~g%20comp.lang.vhdl

comp.lang.verilog http://www.dejanews.com/[ST_rn=bg]/dnquery.xp?query=~g%20comp.lang.verilog

http://www.sandcraft.com/ | http://wpi.supersites.net/ncworldjobbankn2/sandcraft/home.htm | http://supersite.net/techjobsh2/sandcraft/home.htm VLSI jobs ???

The Center for Space Microelectronics Technology (CSMT) http://csmt.jpl.nasa.gov/csmtpages/index.html "The Center concentrates on innovative high-risk, high-payoff concepts and devices ... sensors for [the entire] the electromagnetic spectrum ... microinstruments and microelectronic systems for miniature spacecraft, and high-performance computing both in space and on the ground"

Ultrathin Packaging of Multiple Integrated-Circuit Chips http://www.nasatech.com/TSP/PDFTSP/LEW16545.pdf "total package thickness ... less than 5 thousandths of an inch (5 mils) thick. By comparison, a piece of copy machine paper is roughly 4 mills thick."

Started 1998-06-14

Send comments, suggestions, bug reports to

David Cary

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